--- a/include/seqan/simd.h +++ b/include/seqan/simd.h @@ -87,10 +87,13 @@ #endif // Define maximal size of vector in byte. -#if defined(SEQAN_SEQANSIMD_ENABLED) && defined(__AVX512F__) +#if defined(SEQAN_SEQANSIMD_ENABLED) && defined(__AVX512F__) && defined(COMPILER_GCC) + // gcc compiler supports auto vectorization + #define SEQAN_SIZEOF_MAX_VECTOR 64 +#elif defined(SEQAN_SEQANSIMD_ENABLED) && defined(__AVX512F__) // TODO(marehr): If we switch to jenkins, filter out these warnings #if !(defined(NDEBUG) || defined(SEQAN_ENABLE_TESTING)) - #pragma message("SEQAN_SIMD doesn't support AVX512, thus falling back to AVX2 " \ + #pragma message("SEQAN_SIMD doesn't support AVX512 (except gcc), thus falling back to AVX2 " \ "(we are using some back ported instruction for AVX2 which where introduced since AVX512)") #endif #define SEQAN_SIZEOF_MAX_VECTOR 32 @@ -106,13 +109,17 @@ #include "simd/simd_base_seqan_impl.h" #if defined(SEQAN_SEQANSIMD_ENABLED) - #if defined(__SSE4_2__) + #if SEQAN_SIZEOF_MAX_VECTOR >= 16 #include "simd/simd_base_seqan_impl_sse4.2.h" - #endif // defined(SEQAN_SSE4) + #endif // SEQAN_SIZEOF_MAX_VECTOR >= 16 - #if defined(__AVX2__) + #if SEQAN_SIZEOF_MAX_VECTOR >= 32 #include "simd/simd_base_seqan_impl_avx2.h" - #endif // defined(__AVX2__) + #endif // SEQAN_SIZEOF_MAX_VECTOR >= 32 + + #if SEQAN_SIZEOF_MAX_VECTOR >= 64 + #include "simd/simd_base_seqan_impl_avx512.h" + #endif // SEQAN_SIZEOF_MAX_VECTOR >= 64 #include "simd/simd_base_seqan_interface.h" #endif // defined(SEQAN_SEQANSIMD_ENABLED) --- /dev/null +++ b/include/seqan/simd/simd_base_seqan_impl_avx512.h @@ -0,0 +1,234 @@ +// ========================================================================== +// SeqAn - The Library for Sequence Analysis +// ========================================================================== +// Copyright (c) 2006-2016, Knut Reinert, FU Berlin +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of Knut Reinert or the FU Berlin nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL KNUT REINERT OR THE FU BERLIN BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +// DAMAGE. +// +// ========================================================================== +// Author: Marcel Ehrhardt +// ========================================================================== +// generic SIMD interface for AVX512 +// ========================================================================== + +#ifndef SEQAN_INCLUDE_SEQAN_SIMD_SIMD_BASE_SEQAN_IMPL_AVX512_H_ +#define SEQAN_INCLUDE_SEQAN_SIMD_SIMD_BASE_SEQAN_IMPL_AVX512_H_ + +namespace seqan { + +// SimdParams_<64, 64>: 512bit = 64 elements * 8bit +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector64Char, char, 64) +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector64SChar, signed char, 64) +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector64UChar, unsigned char, 64) + +// SimdParams_<64, 32>: 512bit = 32 elements * 2 * 8bit +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector32Short, short, 64) +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector32UShort, unsigned short, 64) + +// SimdParams_<64, 16>: 512bit = 16 elements * 4 * 8bit +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector16Int, int, 64) +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector16UInt, unsigned int, 64) + +// SimdParams_<64, 8>: 512bit = 8 elements * 8 * 8bit +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector8Int64, int64_t, 64) +SEQAN_DEFINE_SIMD_VECTOR_(SimdVector8UInt64, uint64_t, 64) + +// ============================================================================ +// Functions +// ============================================================================ + +// ============================================================================ +// AVX512 wrappers (512bit vectors) +// ============================================================================ + +// -------------------------------------------------------------------------- +// _fillVector (512bit) +// -------------------------------------------------------------------------- + +template +inline void +_fillVector(TSimdVector & vector, + std::tuple const & x, + std::index_sequence<0> const &, + SimdParams_<64, L>) +{ + vector = createVector(std::get<0>(x)); +} + +template +inline void +_fillVector(TSimdVector & vector, + std::tuple const & args, + std::index_sequence const &, + SimdParams_<64, L>) +{ + using TSimdValue = typename Value::Type; + vector = TSimdVector{static_cast(std::get(args))...}; +} + +// -------------------------------------------------------------------------- +// _clearVector (512bit) +// -------------------------------------------------------------------------- + +template +inline void _clearVector(TSimdVector & vector, SimdParams_<64, L>) +{ + vector = TSimdVector{}; +} + +// -------------------------------------------------------------------------- +// _createVector (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _createVector(TValue const x, SimdParams_<64, L>) +{ + using TValue_ = typename Value::Type; + return TSimdVector{} + static_cast(x); +} + +// -------------------------------------------------------------------------- +// _cmpEq (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _cmpEq(TSimdVector & a, TSimdVector & b, SimdParams_<64, L>) +{ + return a == b; +} + +// -------------------------------------------------------------------------- +// _cmpGt (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _cmpGt(TSimdVector & a, TSimdVector & b, SimdParams_<64, L, TValue>) +{ + return a > b; +} + +// -------------------------------------------------------------------------- +// _bitwiseAndNot (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _bitwiseAndNot(TSimdVector & a, TSimdVector & b, SimdParams_<64, L>) +{ + return (~a & b); +} + +// -------------------------------------------------------------------------- +// _max (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _max(TSimdVector & a, TSimdVector & b, SimdParams_<64, L, TValue>) +{ + return a > b ? a : b; +} + +// -------------------------------------------------------------------------- +// _blend (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _blend(TSimdVector const & a, TSimdVector const & b, TSimdVectorMask const & mask, SimdParams_<64, L>) +{ + return mask ? b : a; +} + +// -------------------------------------------------------------------------- +// _storeu (512bit) +// -------------------------------------------------------------------------- + +template +inline void _storeu(T * memAddr, TSimdVector & vec, SimdParams_<64, L>) +{ + constexpr auto length = LENGTH::VALUE; + for (unsigned i = 0; i < length; i++) + memAddr[i] = vec[i]; +} + +// ---------------------------------------------------------------------------- +// Function _load() 512bit +// ---------------------------------------------------------------------------- + +template +inline TSimdVector _load(T const * memAddr, SimdParams_<64, L>) +{ + constexpr auto length = LENGTH::VALUE; + TSimdVector result; + for (unsigned i = 0; i < length; i++) + result[i] = memAddr[i]; + return result; +} + +// -------------------------------------------------------------------------- +// _shiftRightLogical (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector _shiftRightLogical(TSimdVector const & vector, const int imm, SimdParams_<64, L>) +{ + return vector >> imm; +} + +// -------------------------------------------------------------------------- +// _gather (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector +_gather(TValue const * memAddr, + TSimdVector const & idx, + std::integral_constant const & /*scale*/, + SimdParams_<64, L>) +{ + constexpr auto length = LENGTH::VALUE; + TSimdVector result; + for (unsigned i = 0; i < length; i++) + result[i] = memAddr[idx[i]]; + return result; +} + +// -------------------------------------------------------------------------- +// _shuffleVector (512bit) +// -------------------------------------------------------------------------- + +template +inline TSimdVector1 +_shuffleVector(TSimdVector1 const & vector, TSimdVector2 const & indices, SimdParams_<64, L>, SimdParams_<64, 64>) +{ + constexpr auto length = seqan::LENGTH::VALUE; + TSimdVector1 result{}; + for(unsigned i = 0u; i < length; ++i) + result[i] = vector[indices[i]]; + return result; +} + +} // namespace seqan + +#endif // SEQAN_INCLUDE_SEQAN_SIMD_SIMD_BASE_SEQAN_IMPL_AVX512_H_ --